This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In conventional circuit designs, memory sub-systems are typically restricted by various timing constraints. These memory sub-systems use shadow logic on its output that is followed by a flip-flop. Typical timing conditions are met so that there are no delay faults in the system. However, during testing of shadow logic, multiple conditions should be checked by using design-for-test (DFT) functionality of memory. However, in present designs, only one condition of an operating mode inside the memory is checked. Hence, there is only partial coverage of delay faults during conventional testing.